The invention relates generally to electronic delay lines and, more particularly but not by way of limitation, to the design of adjustable delay lines.
Delay lines are often used by design engineers to adjust the timing of various events in an electronic system. For example, delay lines may be used to adjust or set sampling times in high-speed analog and digital circuits.
A trend in the field of computer system design is the use of source-strobed interfaces. In a source-strobed interface, that component sourcing (transmitting) data also generates and transmits a strobe signal that is used by the receiving component to capture or latch the data. One source-strobed interface is that used by double data rate (DDR) dynamic random access memory devices. (The DDR standard is available from the Joint Electron Device Engineering Counsel as document JESD-21-C.) Memory interface circuits designed to work with Synchlink and RAMBUS(copyright) memory devices are also source-strobed. (A standard defining Synchlink memory has been assigned the tentative designation of IEEE-1596.7 by the Institute of Electrical and Electronics Engineers. The RAMBUS(copyright) standard is published by Rambus, Incorporated of Mountain View, Calif.) Another interface making use of source-strobed techniques is the accelerated graphics port (AGP) interface. (The Accelerated Graphics Port Interface Specification, Rev. 2.0, May 1998, is available from Intel Corporation.)
Referring to FIG. 1, source-strobed interface 100 includes circuit A 102, circuit B 104 (either or both of which may act as a transmitter and receiver of data), data path 106 and strobe path 108. To ensure that data 110 is reliably captured, it is important that the strobe signal""s rising edge 112 (and/or falling edge 114) occur as closexe2x80x94in timexe2x80x94to the data signal""s center 116 as possible. Thus, for optimal performance a source-strobed interface receiver (e.g., circuit B 104) designed to capture data signal 110 on the strobe signal""s rising edge 112 would delay the strobe signal""s rising edge 112 by an amount of time indicated by 118; effectively shifting the strobe""s latching edge into the center of data signal 110 (the xe2x80x9cdata eyexe2x80x9d).
Current embodiments of DDR interfaces operate at 133 MHz (megahertz) to provide a 266 MHz data transfer rate. At these frequencies data strobe 108 has a period of approximately 7.5 nsec (nanoseconds). Due to the allowed timing tolerances between data signal 106 and strobe signal 108, strobe signal 108 may typically need to be delayed up to approximately one-quarter period or 1.5 to 2.0 nsec. Similar delay periods may be required by Synchlink, RAMBUS(copyright) and AGP interface circuitry.
Prior art digital delay lines have typically been designed using inverter chains (inverter units coupled in series) to introduce signal delay and multiplexer trees (multiplexer units arranged in a tiered fashion) to perform selection of the appropriately delayed signal. Referring to FIG. 2, for example, delay line 200 uses inverter chain 202 to generate a sequence of signals, each a differently delayed version of input signal 204 (output from each inverter unit represents a delayed version of its input signal). Multiplexer tree 206 selectively routes (under control of select signal 208) one of the delayed versions of input signal 204 to output port 210. During delay line setup and/or run-time operations, select signal 208 may be modified to route a different delayed version of input signal 204 to output port 210.
Intrinsic delay times through conventional inverter/buffer elements used in semiconductor devices (e.g., standard cell modules used by custom semiconductor device design tools) such as delay line 200 are in the range of 45 to 80 nsec. Thus, it is often difficult to design a delay circuit having the resolution required by current source-strobed interfaces (e.g., in the range of 10 to a few 100 picoseconds). In addition, the use of multiplexer trees complicates delay line design because each leg through a multiplexer typically has a different inherent delay. These differences must be accommodated in the delay line""s ultimate design, often requiring custom layout of each multiplexer unit.
Thus, there is a need for digital delay lines that provide the ability to adjustably delay a signal with a resolution in the range of one to a few hundred picoseconds, are relatively immune to the delay introduced by different legs of a multiplexer (or other signal selection circuit). There is a further need for an adjustable digital delay line providing these benefits that may be constructed from standard cell elements (e.g., buffers, inverters and multiplexer units).
In one embodiment the invention provides a programmable delay circuit that includes a plurality of coarse delay stages (coupled in series fashion) and a fine delay stage having a plurality of parallel organized delay paths. Each of the parallel organized delay paths is adapted to receive input from a common coarse delay stage and to delay a signal for a different specified amount of time. Programmable delay circuits in accordance with the invention may provide a relatively large overall signal delay (provided primarily by the coarse delay stages), while also providing a fine temporal resolution (provided primarily by the fine delay stage). Illustrative uses for a delay circuit in accordance with the invention include, but are not limited to, source-strobed interfaces.